The design of processing architectures is crucial to improving the speed, power and efficiency of digital processing systems. More complex computing systems generally require more innovative architecture design in order to maximize the utility of the available processing power.
One tradeoff that is often made in processing architecture design is the tradeoff between speed, complexity and reconfigurability. For example, where a unit, e.g., an execution unit is highly configurable. There is more of a burden in controlling the unit. A reconfigurable unit needs to receive control signals to set up the configuration. Also, the unit's configuration is dependent on the higher-level tasks that are being performed, or solved, within the overall system.
Thus, it is desirable to provide features for a digital processing architecture that improve upon one or more shortcomings in the prior art.